Given Max Baud Err = 0.75% and Max Timer Drift = 0% | |||||
Clock | Pre Scale |
RTCC Inc |
Max ISR Cycles |
ISR Rate |
Rates, per division w/ percent error
Timing period (min / max), per counter width w/ max drift |
---|---|---|---|---|---|
6.144Mhz | 1 | 235 | 235 | 26.144681Khz | ÷87=300 |
6.144Mhz | 1 | 234 | 234 | 26.256410Khz | ÷11=2400-0.55%, ÷22=1200-0.55%, ÷44=600-0.55%, ÷87=300+0.60%, ÷88=300-0.55% |
6.144Mhz | 1 | 233 | 233 | 26.369099Khz | ÷11=2400, ÷22=1200, ÷44=600, ÷88=300 |
6.144Mhz | 1 | 232 | 232 | 26.482759Khz | ÷11=2400, ÷22=1200, ÷44=600, ÷88=300 |
6.144Mhz | 1 | 231 | 231 | 26.597403Khz | ÷11=2400+0.74%, ÷22=1200+0.74%, ÷44=600+0.74%, ÷88=300+0.74%, ÷89=300 |
6.144Mhz | 1 | 230 | 230 | 26.713043Khz | ÷89=300 |
6.144Mhz | 1 | 229 | 229 | 26.829694Khz | ÷45=600-0.63%, ÷89=300, ÷90=300-0.63% |
6.144Mhz | 1 | 228 | 228 | 26.947368Khz | ÷45=600, ÷90=300 |
6.144Mhz | 1 | 227 | 227 | 27.066079Khz | ÷45=600, ÷90=300 |
6.144Mhz | 1 | 226 | 226 | 27.185841Khz | ÷45=600+0.68%, ÷90=300+0.68%, ÷91=300 |
6.144Mhz | 1 | 225 | 225 | 27.306667Khz | ÷91=300 |
6.144Mhz | 1 | 224 | 224 | 27.428571Khz | ÷23=1200-0.62%, ÷46=600-0.62%, ÷91=300, ÷92=300-0.62% |
6.144Mhz | 1 | 223 | 223 | 27.551570Khz | ÷23=1200, ÷46=600, ÷92=300 |
6.144Mhz | 1 | 222 | 222 | 27.675676Khz | ÷23=1200, ÷46=600, ÷92=300 |
6.144Mhz | 1 | 221 | 221 | 27.800905Khz | ÷23=1200+0.72%, ÷46=600+0.72%, ÷92=300+0.72%, ÷93=300 |
6.144Mhz | 1 | 220 | 220 | 27.927273Khz | ÷93=300 |
6.144Mhz | 1 | 219 | 219 | 28.054795Khz | ÷47=600-0.52%, ÷93=300+0.55%, ÷94=300-0.52% |
6.144Mhz | 1 | 218 | 218 | 28.183486Khz | ÷47=600, ÷94=300 |
6.144Mhz | 1 | 217 | 217 | 28.313364Khz | ÷47=600, ÷94=300, ÷95=300-0.66% |
6.144Mhz | 1 | 216 | 216 | 28.444444Khz | ÷95=300 |