Given Max Baud Err = 0.75% and Max Timer Drift = 0% | |||||
Clock | Pre Scale |
RTCC Inc |
Max ISR Cycles |
ISR Rate |
Rates, per division w/ percent error
Timing period (min / max), per counter width w/ max drift |
---|---|---|---|---|---|
5Mhz | 1 | 255 | 255 | 19.607843Khz | ÷65=300+0.55% |
5Mhz | 1 | 254 | 254 | 19.685039Khz | ÷33=600-0.58%, ÷66=300-0.58% |
5Mhz | 1 | 253 | 253 | 19.762846Khz | ÷33=600, ÷66=300 |
5Mhz | 1 | 252 | 252 | 19.841270Khz | ÷33=600, ÷66=300 |
5Mhz | 1 | 251 | 251 | 19.920319Khz | ÷33=600+0.60%, ÷66=300+0.60% |
5Mhz | 1 | 250 | 250 | 20.000000Khz | ÷67=300 |
5Mhz | 1 | 249 | 249 | 20.080321Khz | ÷67=300 |
5Mhz | 1 | 248 | 248 | 20.161290Khz | ÷67=300 |
5Mhz | 1 | 247 | 247 | 20.242915Khz | ÷67=300+0.71% |
5Mhz | 1 | 246 | 246 | 20.325203Khz | ÷17=1200, ÷34=600, ÷68=300 |
5Mhz | 1 | 245 | 245 | 20.408163Khz | ÷17=1200, ÷34=600, ÷68=300 |
5Mhz | 1 | 244 | 244 | 20.491803Khz | ÷17=1200, ÷34=600, ÷68=300 |
5Mhz | 1 | 243 | 243 | 20.576132Khz | ÷69=300-0.60% |
5Mhz | 1 | 242 | 242 | 20.661157Khz | ÷69=300 |
5Mhz | 1 | 241 | 241 | 20.746888Khz | ÷69=300 |
5Mhz | 1 | 240 | 240 | 20.833333Khz | ÷69=300+0.64% |
5Mhz | 1 | 239 | 239 | 20.920502Khz | ÷35=600, ÷70=300 |
5Mhz | 1 | 238 | 238 | 21.008403Khz | ÷35=600, ÷70=300 |
5Mhz | 1 | 237 | 237 | 21.097046Khz | ÷35=600, ÷70=300 |
5Mhz | 1 | 236 | 236 | 21.186441Khz | ÷71=300-0.54% |