Multiplexers select between sets of inputs. In this case, between the top 4 and the next 4. When the bottom input is 1, the top 4 pass through. When it's 0, the bottom 4 pass.
The select line is fed to the bottom input on a set of 4 NAND gates, the top input of each gate comes from the first 4 inputs to the module. If the select line is off, it doesn't matter what those module inputs are; the outputs of those 4 NAND gates will be 1.
Now look at the 4 NAND gates below those. Their top inputs come from the second set of module input, but the bottom input of each gate comes from an inverted version of the select input. So if the select is off, the inverted select is on, and now, if the top input of each gate is on, the output will go off.
Those two sets of NAND gates are fed into a final output set of NAND gates. Each input to a single gate will be a 1 if that bit is not selected, and a 1 or a 0 from the other bit. The result is.. the original bit of the selected input. Confused? It's easier to see from playing around with the simulation that it is to describe in English.
Remember: It's all done with NANDs!
|file: /Techref/logic/mux4.htm, 1KB, , updated: 2013/4/27 22:58, local time: 2018/12/16 22:11,
|©2018 These pages are served without commercial sponsorship. (No popup ads, etc...).Bandwidth abuse increases hosting cost forcing sponsorship or shutdown. This server aggressively defends against automated copying for any reason including offline viewing, duplication, etc... Please respect this requirement and DO NOT RIP THIS SITE. Questions?|
<A HREF="http://www.sxlist.com/techref/logic/mux4.htm"> Digital Logic Tutorial - A 4 bit multiplexer</A>
|Did you find what you needed?|
Welcome to sxlist.com!
& kind contributors
just like you!
Please don't rip/copy
Copies of the site on CD
are available at minimal cost.
Welcome to www.sxlist.com!